This invention relates to a structure of a cache memory of a processor, and more particularly, to a technique of cache memory construction that includes stacking a plurality of large scale integrations (LSI).
Device miniaturization owing to the recent advancement in semiconductor manufacture technology has made it possible to integrate numerous transistors on one die, and now a few or many processor cores can be integrated on one die or in one package. Multi-core processors having a plurality of processor cores, for example, have an exponentially improved computing ability.
Meanwhile, the transfer rate of DRAMs widely employed as a main memory which stores data read and written by a processor has not kept up with the aforementioned improvement in processing ability of processors, thus causing a large latency when the processor accesses the main memory. A technique widely employed as a countermeasure in recent processors is to lower the frequency of direct access to the main memory from a processor core by mounting a Level 2 (L2) or Level 3 (L3) cache to the same die or the same package as the processor core (for example, JP 2000-68460 A or the IBM's Power series).
Another popular technique of reducing the latency in access to the main memory from the processor core is to mount a memory controller onto the die (on-die memory controllers).
As described above, increasing the capacity of the L2 or L3 cache makes the processor core access the main memory less frequently, but the on-die L2 or L3 cache has a problem in that the yield of processor products is lowered in proportion to the increase in area of the die due to the added L2 or L3 cache.
As a solution to this problem, a technique has been proposed which divides LSIs constituting a processor into layers and stacks the LSIs on top of one another to make them into a single package (an example is found in an online research paper titled “Design and Management of 3D Chip Multiprocessors Using Network in Memory”, written by Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, and Mahmut Kandemir, Dept. of CSE, The Pennsylvania State University. According to the technique of this document (hereinafter referred to as Non-patent Document 1), an electrode that pierces the LSIs divided into layers in the sectional direction (called a through electrode) connects the stacked LSIs to one another. A processor core and an L2 cache memory are provided in each of the LSIs divided into layers, and the layers are stacked together to constitute one processor.